The present invention relates to a liquid crystal image display apparatus; and, more particularly, the invention relates to a liquid crystal image display apparatus which can display an image with low power consumption.
A conventional image display apparatus will be described with reference to FIG. 19, which is a diagram showing the construction of a TFT liquid crystal panel using conventional technology. Pixels 100 each having a liquid crystal capacitor 101 and a pixel switch 102 are arranged in the form of a matrix, and a gate of the pixel switch 102 is connected to a gate line shift register 104 through a gate line 103. Further, a drain of the pixel switch 102 is connected to a DA converter 106 through a signal line 105. On the other hand, each of memory cells of a frame memory arranged in the form of a matrix is composed of a memory capacitor 111 and a memory switch 112, and a gate of the memory switch is connected to a word line shift register 114 through a word line 113 and a word line selection switch 115 arranged at the end of the word line. On the other hand, one end of each of the memory switches is connected to a data line 116. A data input circuit 117 is arranged at one end of the data line 116, and a sense amplifier 108 and a latch circuit 107 are arranged at the other end of the data line 116. An output of the latch circuit 107 is connected to the DA converter 106. The above-described constituent elements are formed using poly-Si TFT on a single substrate.
The operation of the TFT liquid crystal panel will be described. At the time of writing, image data from the data input circuit 117 is written in the memory cells on a row selected by the word line shift register 114 and the word line selection switch 115, similar to a general DRAM (dynamic random access memory). Similarly, the image data of the memory cells on the row selected by the word line shift register 114 and the word line selection switch 115 is input to the sense amplifier 108 through the data line 116 so as to be latched by the latch circuit 107. The latched image data is converted to an analogue signal by the DA converter 106 and is output to the signal line 105. At that time, the gate line shift register 104 is scanned in synchronism with the word line shift register 114, and the gate line shift register 104 sets the pixel switch 102 on a given row to the ON-state through the gate line 103. Thereby, the analogue signal is written in the liquid crystal capacitor 101 of the given pixel 100, and, accordingly, the image can be displayed using the liquid crystal based on the read-out image data.
The above-described apparatus is described in detail, for example, in Japanese Patent Application Laid-open No. 11-85065 (1999).
According to the conventional technology described above, by driving the word line 113 of the frame memory and the gate line 103 of the pixel portion with an equal driving frequency, it is possible to avoid interference noise caused by leaking of a word line clock signal of the frame memory into the displayed image. However, low power consumption of the image display apparatus is not sufficiently taken into consideration. This problem will be described below.
From the viewpoint of improving the yield by reducing the area and the number of pixels, the frame memory is not formed by a SRAM (static random access memory), but is typically formed by a DRAM, as described above. However, when a general DRAM cell structure, which is typically composed of one transistor and one capacitor, is used, a circuit having a large penetration current can not help being employed as the sense amplifier 108, because it is necessary to amplify a very small signal below several tens mV. This is a big problem from the viewpoint of low power consumption of the device.
Further, from the viewpoint of driving the DRAM cell, in contrast to the conventional example in which writing, refreshing and reading are separately considered, power consumption must be further reduced by organically combining writing, refreshing and reading or by modifying the driving method.